1. Technical Field
This disclosure relates generally to improved embedded semiconductor products and methods and apparatus for making such semiconductor products.
2. Related Art
A non-volatile memory cell in a non-volatile core array is programmed using, for example, hot carrier injection to place change into a storage layer. High drain and gate voltages are used to facilitate the programming process, and the memory cell conducts relatively high current during programming, which can be undesirable in low voltage or low power applications.
A split-gate non-volatile memory cell is a type of non-volatile memory cell, in which a select gate is placed adjacent a memory gate. During programming of a split gate non-volatile memory cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. That makes hot-carrier injection more efficient during programming operation compared to conventional non-split gate memory cell. A split-gate non-volatile memory cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional non-volatile memory cell during programming operation may vary.
Fast read time is another advantage of a split-gate non-volatile memory cell. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erased state near or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between erased and programmed states. Accordingly, the voltages applied to both select gate and memory gate in read operation can be less than or equal to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
It is common to monolithically incorporate multiple types of field-effect devices on the same substrate as the memory cells. Those devices perform, for example, decoding, charge-pumping, and other functions related to memory operations. The substrate may also include devices to provide functions that are not, related to memory operations. Such non-memory devices incorporated on the same substrate as the memory cells may include transistors tailored for high-speed operations, while other transistors are tailored for handling high operating voltages. Integrating the processing of memory cells, such as a split-gate non-volatile memory cell, with the processing of one or more types of non-memory transistors on the same substrate is challenging as each requires different fabrication parameters. For example, for high speed performance requirement, the gate length of the non-memory transistors needs to be shorter such that it requires thinner gate stack for easier processing. However, for non-memory transistors to handle higher operating voltages, the junction of the transistors needs to be more graded. This usually is accomplished by higher implantation energy during the junction formation. Thicker gate stack is needed to prevent implant penetration. Therefore, it is desirable to have a method to have different gate stack thickness for different non-memory transistors and integrate with non-volatile memory cells on the same semiconductor device. Accordingly, there is a need for device and methods for integrating a memory cell and other devices with different electrical requirements on the same substrate to facilitate improved cost, performance, reliability, or manufacturability.